1. Field of the Invention
Embodiments of the present invention relate generally to protecting boot block space in NAND memory devices.
2. Description of the Related Art
A serial peripheral interface (SPI) is a communication interface that provides a synchronous serial data link between a master device and a slave device. SPI provides support for a low to medium bandwidth network connection amongst processors and other devices.
The SPI bus includes four wires including of two control lines and two data lines. The control lines include a Serial Clock (SCK) line and a Chip Select (CS) line. The SCK signal is used to clock the shifting of serial data simultaneously into and out of the master and slave devices, allowing the SPI architecture to operate as a full duplex protocol. The CS line is driven with a signal that enables or disables the slave device being controlled by the master device. Furthermore, the master device may communicate with additional slave devices, although an additional CS line is required for each additional slave device.
SPI data lines include a Serial Data Out (SO) line and a Serial Data In (SI) line. The SO line is a data communication line that transfers data from an output of the slave device to an input of the master device. Similarly, the SI line is a data communication line that transfers data from the output of the master device to the input of the slave device. The SO and SI lines are active when the CS signal for a specific slave device transitions to an enabling state, typically active low.
Because SPI utilizes only four lines of communication, SPI has become increasingly advantageous for use in systems that require relatively simple IC designs. For example, devices which have been configured to communicate using SPI include several types of nonvolatile memory devices, including EEPROM and NOR flash memory. The SPI's relatively simple configuration of control and data lines allows for a relatively high board density at a low cost. For example, SPI EEPROM devices allow for ICs with as few as 8 pins, whereas conventional EEPROM devices may require 32 or more pins. Similarly, SPI NOR flash memory also allows ICs with substantially fewer pins than conventional NOR memory devices. Accordingly, SPI may be advantageous for use in applications desiring compact and simple layouts, such as computers.
Computer systems and other electrical systems generally include one or more memory devices. For example, computers often employ NOR flash memory and NAND flash memory. NOR and NAND flash each have certain advantages over the other. For example, NOR flash memory typically has slower write and erase speeds than NAND flash. Further, NAND flash memory typically has more endurance than NOR flash memory. However, NOR flash memory typically enables random access to data stored within the memory devices, whereas, NAND flash memory generally operates by accessing and writing data in larger groups. For example, NAND flash memory typically includes a plurality of blocks. Each block includes a plurality of pages that each includes a large number of bytes of data. During NAND flash memory operation, data is erased one block at a time and written one page at a time.
Memory arrays are generally divided into several blocks, each block including a plurality of pages of data. The memory array may also include one or more boot blocks. Boot blocks are typically smaller in size compared to the main data blocks and are used to store sensitive data, for example, boot code. Although some memory devices may include only a single boot block, as computing technology has advanced, boot code for computing devices has also increased in size, thus driving the need for increased boot block space. Because of the often sensitive nature of the data stored in the boot blocks, there is a need for security mechanisms to limit access to boot block data.
Embodiments of the present invention may be directed to one or more of the problems set forth above.